Business Wire

Keysight Introduces PCIe Designer and Chiplet PHY Designer for Digital Standards-Driven Simulation Workflows

Improves PCIe design productivity using a smarter and streamlined workflow with simulation-driven virtual compliance test solutions Supports design exploration and report generation that speeds ...
Business Wire

Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support Down to 5nm, and Simulation-Driven Layout

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced major enhancements to its Cadence ® Virtuoso ® custom IC design platform that improve electronic system ...
Nasdaq

Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its PHY and Controller IP for the PCI Express® (PCIe®) 5.0 specification in the TSMC N7, N6 and N5 ...
Semiconductor Engineering

What Is Electronic Design Automation And Why Do You Need It?

As data speeds push into the multi-gigabit range and requirements on digital systems grow more complex, cutting down the time-to-market while also ensuring error-free reliable designs seems impossible ...
EDN

ADS improvements for DDR5 simulation

Keysight’s PathWave Advanced Design System (ADS) 2023 for high-speed digital design includes improvements for DDR5 simulation. In addition to DDR5, the new Memory Designer capabilities in PathWave ...