Duke Pratt School of Engineering

Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

Duke engineers show how a common device architecture used to test 2D transistors overstates their performance prospects in ...
Semiconductor Engineering

Improving Gate All Around Transistor Performance Using Virtual Process Window Exploration

As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF [1]. One method to overcome this problem is to move away from planar ...
Interesting Engineering on MSN

China claims to develop world’s smallest and most energy-efficient transistor

Researchers at Peking University in China have developed the world’s smallest and most energy-efficient ...
Nanowerk

Common lab design inflates 2D transistor performance by up to six times

Lab architecture used to test 2D semiconductors artificially boosts performance metrics, making it harder to assess whether ...
Compound Semiconductor

Has 2D transistors' performance been inflated?

The research 'Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure' appeared ...
Semiconductor Engineering

The Impact Of Metal Gate Recess Profile On Transistor Resistance And Capacitance

In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize ...