EDN

Frequency and phase locked loops

The purpose of a phase locked loop (PLL) is to generate a frequency and phase-locked output oscillation signal. To achieve this goal, prior art essentially functioned ...
Design-Reuse

Low Power High Speed All Digital Phase Locked Loops

In this paper an All Digital phase locked loop is proposed. This PLL can accomplish faster phase lock. Additionally, the functions of frequency comparator and phase detector have been improved and are ...
EDN

Determining the angle resolution of all-digital PLL-based resolver-to-digital converters

A resolver is a sensor that estimates the angle of a rotating shaft, such as the shaft of an electrical motor used in automotive traction inverter applications. To obtain a digital representation of ...
Electronics Weekly

A tiny useful discovery about the 4046 phase locked loop chip

Whilst poring over 4046 phase locked loop data sheets, I noticed yet another subtle useful difference between the the later faster 74HC4046 (diag from NXP data sheet) and the earlier slower CD4046.