Alibaba delivers RISC-V server chip optimized to run China’s top AI models

Alibaba has revealed a new server chip that it says is the most powerful processor ever to use the RISC-V instruction set.
AppleInsider

Apple investigating RISC-V instruction set architecture, job listing shows

A job listing posted to Apple's website this week reveals the company is researching RISC-V instruction set architecture solutions, suggesting future in-house chip designs might implement the ...
Blockonomi

Linea Ends Direct EVM Arithmetization, Moves to RISC-V to Match Ethereum’s Proving Roadmap

Linea, the Ethereum Layer 2 network developed by ConsenSys, is transitioning from direct EVM arithmetization to a RISC-V-based proving architecture. The team spent three years building one of the most ...
Guru3D

Samsung Prepares PCIe 5.0 QLC SSD with Custom RISC-V Controller Design

Samsung is taking a notable step in SSD controller development by introducing a proprietary design based on the RISC-V instruction set. The new controller debuts in the upcoming BM9K1 PCIe 5.
Electronic Design

RISC-V: The Instruction-Set Alternative

First and foremost, RISC-V is a modular, open-source, instruction set definition and nothing more. RISC-V as an ecosystem is much more. The instruction set provides the encoding and semantics, but it ...
Semiconductor Engineering

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases

This new technical paper titled “Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms” was published by researchers at Intel, North Arizona University and Google, with ...
Semiconductor Engineering

Extending RISC-V ISA With Custom Instruction Set Extension

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...
Morning Overview on MSN

Samsung readies PCIe 5.0 QLC SSD with a RISC-V based controller

Samsung is preparing a PCIe 5.0 SSD that pairs quad-level cell (QLC) flash memory with a RISC-V-based controller, a ...
Design-Reuse

RISC-V set to announce 25% market penetration - open-standard ISA is ahead of schedule, securing fast-growing silicon footprint

ARM has some competition in the reduced-complexity chip space, and it's gaining ground quickly. RISC-V International plans to announce that silicon on the open-standard has reached 25% market ...
Hackaday

Compute The Mandelbrot Set With A Custom RISC-V CPU

When faced with an FPGA, some people might use it to visualize the Mandelbrot set. Others might use it to make CPUs. But what happens if you combine the two? [Michael Kohn] shows us what happens with ...
Hackaday

SiFive Announces RISC-V SoC

At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux ...
Nasdaq

The Industry’s First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture is Now Available

Microchip’s PolarFire® SoC FPGA Icicle Kit enables the broad RISC-V-based Mi-V ecosystem for the industry’s lowest-power FPGA CHANDLER, Ariz., Sept. 16, 2020 (GLOBE NEWSWIRE) -- The rising adoption of ...