Semiconductor Engineering

Overview Of Security Verification Methodologies for SoC Designs Pre-Silicon (U. of Florida)

A technical paper titled “A Survey on SoC Security Verification Methods at the Pre-silicon Stage” was recently published by researchers at University of Florida. “This paper presents a survey of the ...
Semiconductor Engineering

Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions

“The ever-increasing usage and application of system-on-chips (SoCs) has resulted in the tremendous modernization of these architectures. For a modern SoC design, with the inclusion of numerous ...
Business Wire

Cadence Announces Full DRAM Verification Solution for Automotive, Data Center, and Mobile Applications

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a new DRAM verification solution, allowing customers to test and optimize system-on-chip (SoC) designs ...
EDN

Interconnect (NoC) verification in SoC design: Part 3

In our previous blog, we mentioned that verifying an NoC system goes far beyond transaction route checking. We were able to catch various issues during a complex interconnect verification at SoC level ...
Electronic Design

What’s the Deal with SoC Verification?

The title of this article may sound like the start of a Seinfeld joke from the 90s, but it’s actually a serious question. Many people do not appreciate what makes a system-on-chip (SoC) different from ...
EDN

A next-gen FPGA-based SoC verification platform

System-on-Chip (SoC) designs continue to increase in size and complexity. At the same time, market windows are shrinking and today's electronic markets are extremely sensitive to time-to-market ...