Device test times also are rising dramatically. Longer test times are driven by higher levels of embedded memory, higher functionality, higher quality requirements, and the need to move more tests to ...

The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly ...

Test strategy analysis has become increasingly important for finding ways to reduce test costs for system-on-a-chip (SoC) semiconductor devices. Every SoC device’s test flow is unique and requires a ...

SANTA CLARA, Calif.–Looking to reduce the soaring costs of IC test, Intel Corp. hopes to leverage its “casual learning algorithm” technology for wafer sort applications in the fab. Intel is looking to ...

Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to ...